SuperH (SH)
DesignerHitachi Ltd.
Bits32-bit (32 → 64)
EncodingSH2: 16-bit instructions; SH2A and newer: mixed 16- and 32-bit instructions
OpenYes, and royalty free[1]

SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.

At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. This was a novel approach; at the time, RISC processors always used an instruction size that was the same as the internal data width, typically 32-bits. Using smaller instructions had consequences, the register file was smaller and instructions were generally two-operand format. But for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency.

Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a compressed instruction set and is also used by other companies, the most notable example being ARM for its Thumb instruction set.

As of 2015, many of the original patents for the SuperH architecture are expiring and the SH-2 CPU has been reimplemented as open source hardware under the name J2.

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