Reduced instruction set computer


The Sun Microsystems UltraSPARC processor is a type of RISC microprocessor.

In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer in order to realise a task. Unlike the instructions given to a complex instruction set computer (CISC), with a RISC computer, a task might require more instructions (code) in order to realise a task, because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular, implementing an instruction pipeline may be simpler given simpler instructions.[1]

The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate from the instructions that grant access to the main memory of the computer. The design of the CPU allows RISC computers few simple addressing modes[2] and predictable instruction times that simplify design of the system as a whole.

The conceptual developments of the RISC computer architecture began with the IBM 801 project in the late 1970s, but these were not immediately put into use. Designers in California picked up the 801 concepts in two seminal projects, Stanford MIPS and Berkeley RISC. These were commercialized in the 1980s as the MIPS and SPARC systems. IBM eventually produced RISC designs based on further work on the 801 concept, the IBM POWER instruction set architecture, PowerPC, and Power ISA. As the projects matured, many similar designs, produced in the late 1980s and early 1990s, created the central processing units that increased the commercial utility of the Unix workstation and of embedded processors in the laser printer, the router, and similar products.

The varieties of RISC processor design include the ARC processor, the DEC Alpha, the AMD Am29000, the ARM architecture, the Atmel AVR, Blackfin, Intel i860, Intel i960, LoongArch, Motorola 88000, the MIPS architecture, the PA-RISC, the Power ISA, the RISC-V, the SuperH, and the SPARC. RISC processors are used in supercomputers, such as the Fugaku.[3]

  1. ^ Berezinski, John. "RISC: Reduced Instruction set Computer". Department of Computer Science, Northern Illinois University. Archived from the original on 28 February 2017.
  2. ^ Flynn, Michael J. (1995). Computer Architecture: Pipelined and Parallel Processor Design. pp. 54–56. ISBN 0867202041.
  3. ^ "Japan's Fugaku gains title as world's fastest supercomputer". RIKEN. Retrieved 24 June 2020.

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