RISC-V


RISC-V
RISC-V-logo.svg
DesignerUniversity of California, Berkeley
Bits
Introduced2010
Version
  • unprivileged ISA 20191213,[1]
  • privileged ISA 20190608[2]
DesignRISC
TypeLoad-store
EncodingVariable
BranchingCompare-and-branch
EndiannessLittle[1]: 9 [3]
Page size4 KiB
Extensions
  • M: Multiplication
  • A: Atomics — LR/SC & fetch-and-op
  • F: Floating point (32-bit)
  • D: FP Double (64-bit)
  • Q: FP Quad (128-bit)
  • Zicsr: Control and status register support
  • Zifencei: Load/store fence
  • C: Compressed instructions(16-bit)
OpenYes, and royalty free
Registers
General purpose
  • 16
  • 32
(including one always-zero register)
Floating point
  • 32 (F extension)
  • 64 (D extension)
  • 128 (Q extension) (optional)

RISC-V (pronounced "risk-five"[1]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

As a RISC architecture, the RISC-V ISA is a load–store architecture. Its floating-point instructions use IEEE 754 floating-point. Notable features of the RISC-V ISA include bit patterns to simplify the multiplexers in a CPU,[1]: 17  a design that is architecturally neutral, and most-significant bits of immediate values placed at a fixed location to speed sign extension.[1]: 17  The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be any number of 16-bit parcels in length.[1]: 7–10  Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

The instruction set specification defines 32-bit and 64-bit address space variants. The specification includes a description of a 128-bit flat address space variant, as an extrapolation of 32 and 64 bit variants, but the 128-bit ISA remains "not frozen" intentionally, because there is yet so little practical experience with such large memory systems.[1]: 41 

The project began in 2010 at the University of California, Berkeley, but now many current contributors are volunteers not affiliated with the university.[4] Unlike other academic designs which are typically optimized only for simplicity of exposition, the designers intended that the RISC-V instruction set be usable for practical computers.

As of June 2019, version 2.2 of the user-space ISA[5] and version 1.11 of the privileged ISA[2] are frozen, permitting software and hardware development to proceed. The user-space ISA, now renamed the Unprivileged ISA, was updated, ratified and frozen as version 20191213.[1] An external debug specification is available as a draft, version 0.13.2.[6]

  1. ^ a b c d e f g h Cite error: The named reference isa20191213 was invoked but never defined (see the help page).
  2. ^ a b Cite error: The named reference priv-isa was invoked but never defined (see the help page).
  3. ^ Big and bi-endianness supported as extensions
  4. ^ Cite error: The named reference contributors was invoked but never defined (see the help page).
  5. ^ Cite error: The named reference isa2.2 was invoked but never defined (see the help page).
  6. ^ Cite error: The named reference external-debug was invoked but never defined (see the help page).

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