PA-RISC


PA-RISC (HP/PA)
PA-RISC logo.png
DesignerHewlett-Packard
Bits64-bit (32→64)
Introduced1986 (1996 PA-RISC 2.0)
Version2.0 (1996)
DesignRISC
EncodingFixed
BranchingCompare and branch
EndiannessBig
ExtensionsMultimedia Acceleration eXtensions (MAX), MAX-2
OpenNo
Registers
General purpose32
Floating point32 64-bit (16 64-bit in PA-RISC 1.0)
HP PA-RISC 7300LC microprocessor
HP 9000 C110 PA-RISC workstation booting Debian GNU/Linux

PA-RISC is an instruction set architecture (ISA) developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer (RISC) architecture, where the PA stands for Precision Architecture. The design is also referred to as HP/PA for Hewlett Packard Precision Architecture.

The architecture was introduced on 26 February 1986, when the HP 3000 Series 930 and HP 9000 Model 840 computers were launched featuring the first implementation, the TS1.[1][2]

PA-RISC has been succeeded by the Itanium (originally IA-64) ISA, jointly developed by HP and Intel.[3] HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but supported servers running PA-RISC chips until 2013.[4]

  1. ^ "One Year Ago". (26 February 1987). Computer Business Review.
  2. ^ Rosenbladt, Peter (September 1987). "In this Issue" (PDF). Hewlett-Packard Journal. 38 (9): 3. ... In the March 1987 issue we described the HP 3000 Series 930 and HP 9000 Model 840 Computers, which were HP's first realizations of HP Precision Architecture in off-the-shelf TTL technology. ...
  3. ^ HP Completes Its PA-RISC Road Map With Final Processor Upgrade
  4. ^ How long will HP continue to support HP 9000 systems?

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