OpenRISC


OpenRISC
DesignerOriginally Damjan Lampret, now the OpenRISC Community (Stafford Horne etc.)
Bits32-bit, 64-bit
Introduced2000 (2000)
Version1.3[1]
DesignRISC
EncodingFixed
EndiannessBig; unimplemented stub for Little
Page size8 KiB
ExtensionsORFPX32/64,[2] ORVDX64[3]
OpenYes (LGPL / GPL), hence royalty free
Registers
General purpose16 or 32
Floating pointOptional

OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.

The first (and as of 2019 only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support.[4] The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL).[5]
The later mor1kx implementation, which has some advantages compared to the OR 1200,[6] was designed by Julius Baxter and is also written in Verilog.
Additionally software simulators exist,[7] which implement the OR1k specification.

The hardware design was released under the GNU Lesser General Public License (LGPL), respectively the Open Hardware Design License (OHDL), while the models and firmware were released under the GNU General Public License (GPL).

A reference system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs),[8][9] and there have been several commercial derivatives produced.

Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are FuseSoC, minSoC, OpTiMSoC and MiSoC.[10]

  1. ^ "Published versions". Retrieved 2021-03-28.
  2. ^ "Floating point extensions operating on 32-bit/64-bit". Retrieved 2021-03-28.
  3. ^ "Vector/DSP extensions (SIMD) operating on 8-, 16-, 32- and 64-bit data". Retrieved 2021-03-28.
  4. ^ OpenRisc.io https://openrisc.io/architecture. Retrieved 2021-04-17. Missing or empty |title= (help)
  5. ^ Clarke, Peter (2000-02-28). "Free 32-bit processor core hits the Net". Electronic Engineering Times (EE Times). San Francisco, California, United States: AspenCore Media. Retrieved 2019-03-21.
  6. ^ OpenRisc.io https://openrisc.io/implementations#mor1kx. Retrieved 2021-04-17. Missing or empty |title= (help)
  7. ^ OpenRisc.io https://openrisc.io/implementations#system-simulators. Retrieved 2021-04-17. Missing or empty |title= (help)
  8. ^ Pelgrims, Patrick; Tierens, Tom; Driessens, Dries (2004). "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGAs" (PDF). De Nayer Instituut. 1.0. Archived from the original (PDF) on 2006-11-27. Retrieved 2009-03-03.
  9. ^ Li, Xiang; Zuo, Lin. Open source embedded platform based on OpenRISC and DE2-70 (Masters). KTH Royal Institute of Technology (KTH), Sweden. Archived from the original on 2011-10-06., SoC program
  10. ^ OpenRisc.io https://openrisc.io/soc. Retrieved 2021-04-17. Missing or empty |title= (help)

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