IA-64


Intel Itanium architecture
DesignerHP and Intel
Bits64-bit
Introduced2001
DesignEPIC
TypeRegister-Register
EncodingFixed
BranchingCondition register
EndiannessSelectable
Registers
General purpose128 (64 bits plus 1 trap bit; 32 are static, 96 use register windows); 64 1-bit predicate registers
Floating point128
The Intel Itanium architecture

IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was evolved and then implemented in a new processor microarchitecture by Intel with HP's continued partnership and expertise on the underlying EPIC design concepts. In order to establish what was their first new ISA in 20 years and bring an entirely new product line to market, Intel made a massive investment in product definition, design, software development tools, OS, software industry partnerships, and marketing. To support this effort Intel created the largest design team in their history and a new marketing and industry enabling team completely separate from x86. The first Itanium processor, codenamed Merced, was released in 2001.

The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle.

In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC.[1]

  1. ^ Morgan, Timothy (2008-05-27). "The Server Biz Enjoys the X64 Upgrade Cycle in Q1". IT Jungle. Retrieved 2008-10-29.

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