ARM architecture family

Arm logo 2017.svg
Bits32-bit, 64-bit
Introduced1985 (1985)
BranchingCondition code, compare and branch
ARM 64/32-bit
Introduced2011 (2011)
VersionARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8-R, ARMv9
EncodingAArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1]
EndiannessBi (little as default)
ExtensionsSVE, SVE2, SME, AES, SHA, TME; All mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4; obsolete: Jazelle
General purpose31 × 64-bit integer registers[1]
Floating point32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography
ARM 32-bit (Cortex)
VersionARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M
Encoding32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.
EndiannessBi (little as default)
ExtensionsThumb-2, Neon, Jazelle, AES, SHA, DSP, Saturated, FPv4-SP, FPv5, Helium
General purpose15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)
Floating pointUp to 32 × 64-bit registers,[2] SIMD/floating-point (optional)
ARM 32-bit (legacy)
VersionARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
Encoding32-bit, except Thumb extension uses mixed 16- and 32-bit instructions.
EndiannessBi (little as default) in ARMv3 and above
ExtensionsThumb, Jazelle
General purpose15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)
Floating pointNone

ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured for various environments. Arm Ltd. develops the architectures and licenses them to other companies, who design their own products that implement one or more of those architectures, including system on a chip (SoC) and system on module (SOM) designs, that incorporate different components such as memory, interfaces, and radios. It also designs cores that implement these instruction set architectures and licenses these designs to many companies that incorporate those core designs into their own products.

There have been several generations of the ARM design. The original ARM1 used a 32-bit internal structure but had a 26-bit address space that limited it to 64 MB of main memory. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[3] Arm Ltd. has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improved code density, while Jazelle added instructions for directly handling Java bytecode. More recent changes include the addition of simultaneous multithreading (SMT) for improved performance or fault tolerance.[4]

Due to their low costs, minimal power consumption, and lower heat generation than their competitors, ARM processors are desirable for light, portable, battery-powered devices, including smartphones, laptops and tablet computers, and other embedded systems.[5][6][7] However, ARM processors are also used for desktops and servers, including the world's fastest supercomputer in 2020 (Fugaku).[8] With over 200 billion ARM chips produced,[9][10][11] as of 2021, ARM is the most widely used family of instruction set architectures (ISA) and the ISAs produced in the largest quantity.[12][6][13][14][15] Currently, the widely used Cortex cores, older "classic" cores, and specialised SecurCore cores variants are available for each of these to include or exclude optional capabilities.

  1. ^ a b c Cite error: The named reference v8arch was invoked but never defined (see the help page).
  2. ^ "Procedure Call Standard for the ARM Architecture" (PDF). Arm Holdings. 30 November 2013. Retrieved 27 May 2013.
  3. ^ "ARM Discloses Technical Details of the Next Version of the ARM Architecture" (Press release). Arm Holdings. 27 October 2011. Archived from the original on 1 January 2019. Retrieved 20 September 2013.
  4. ^ "Announcing the ARM Neoverse N1 Platform". Retrieved 8 April 2020.
  5. ^ "Some facts about the Acorn RISC Machine" Roger Wilson posting to comp.arch, 2 November 1988. Retrieved 25 May 2007.
  6. ^ a b Hachman, Mark (14 October 2002). "ARM Cores Climb into 3G Territory". ExtremeTech. Retrieved 24 May 2018.
  7. ^ Turley, Jim (18 December 2002). "The Two Percent Solution". Embedded. Retrieved 24 May 2018.
  8. ^ Cutress, Ian (22 June 2020). "New #1 Supercomputer: Fujitsu's Fugaku and A64FX take Arm to the Top with 415 PetaFLOPs". Retrieved 25 January 2021.
  9. ^ "Arm Partners Have Shipped 200 Billion Chips". Arm (Press release). Retrieved 3 November 2021.
  10. ^ "Architecting a smart world and powering Artificial Intelligence: ARM". The Silicon Review. 2019. Retrieved 8 April 2020.
  11. ^ "Enabling Mass IoT connectivity as ARM partners ship 100 billion chips". Retrieved 8 April 2020. the cumulative deployment of 100 billion chips, half of which shipped in the last four years. [..] why not a trillion or more? That is our target, seeing a trillion connected devices deployed over the next two decades.
  12. ^ "MCU Market on Migration Path to 32-bit and ARM-based Devices: 32-bit tops in sales; 16-bit leads in unit shipments". IC Insights. 25 April 2013. Retrieved 1 July 2014.
  13. ^ Turley, Jim (2002). "The Two Percent Solution".
  14. ^ "Arm Holdings eager for PC and server expansion". The Register. 1 February 2011.
  15. ^ McGuire-Balanza, Kerry (11 May 2010). "ARM from zero to billions in 25 short years". Arm Holdings. Retrieved 8 November 2012.

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